Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to manufacturing approaches used in interconnect formation for integrated circuits and other devices.
Related Art
The semiconductor manufacturing process typically includes two major components, namely the Front-End-of-Line (FEOL), which includes the multilayer process of forming semiconductor devices (transistors, etc.) on a semiconductor substrate, and the Back-End-Of-Line (BEOL), which includes the metallization after the semiconductor devices have been formed. Like all electronic devices, semiconductor devices in a microchip, such as an integrated circuit (IC), need to be electronically connected through wiring. In an integrated circuit, such wiring is done through multilayer metallization on top of the multilayered semiconductor devices formed on the semiconductor substrate. The complexity of this wiring becomes appreciable as there may be hundreds of millions or more semiconductor devices (e.g., transistors in particular) formed on a single IC. Proper connection of these devices is accomplished by multilayer metallization. Each metallization layer consists of a grid of metal lines sandwiched between one or more dielectric layers for electrical integrity. Modern semiconductor manufacturing processes can involve multiple metallization layers.
As scaling of microelectronic devices approaches sub 30 nm nodes, many material and module process challenges in BEOL patterning have been reported. In one conventional approach, a BEOL integration scheme uses chemical mechanical planarization (CMP) to remove ruthenium (Ru) layer(s). The prior art device of FIGS. 1-3 demonstrates this process. As shown in FIG. 1, a device 1 comprises a substrate 2, a capping layer 4 formed over substrate 2, a dielectric layer 6 formed over capping layer 4, a Tantalum (Ta)/Tantalum Nitride (TaN) layer 8 formed over dielectric layer 6, a Ruthenium (Ru) layer 10 formed over Ta/TaN layer 8, and a copper (Cu) layer 12 formed over Ru layer 10. As shown in FIG. 2, Cu layer 12 is removed using CMP. As shown in FIG. 3, Ru layer 10 is removed using CMP, along with Ta/TaN layer 8, Cu layer 12, and dielectric layer 6. However, Ru is difficult to remove using CMP due to its slow removal rate. Highly abrasive slurries need to be used to get appreciable CMP removal rate, which in turn result in high defects post-CMP (e.g., scratches, surface particles, etc.). Additionally, expensive post-CMP cleaning chemistries are required to clean the wafer after the CMP. As such, current art approaches are inadequate for at least one of the reasons described above.